The present disclosure relates to a semiconductor structure, and particularly to fin field effect transistors including a tapered vertical cross-sectional area and a method of manufacturing the same.
As scaling of complementary metal oxide semiconductor (CMOS) devices continues, control of the channel through conventional means such as doping profile control and gate dielectric scaling becomes increasingly challenging. A few categories of devices such as fin field effect transistors, trigate transistors, and nanowire transistors circumvent the short channel behavior due to scaling.